VL16 · Sem 5 · VLSI design
Clock divider and PWM generator
Aim: Generate a slower clock and a PWM signal from a counter.
🧪 Live simulation🧊 Real-time 3D bench⚠ Simulated values, not physical measurements
🔬 Virtual lab
Starting the lab…
📘 Theory
A free-running counter divides the clock; comparing it with a duty register gives PWM. This is how FPGAs dim LEDs and drive motors.
duty fraction = duty / 16
🧰 Apparatus (virtual)
- Yosys
- simulator
📝 Procedure
🎤 Viva questions
What sets the PWM frequency
Clock frequency divided by the counter range.
Why is PWM resolution limited
The counter has a fixed number of steps.
🛡️ Safety
Software only. Area and timing use generic teaching assumptions; they are not silicon measurements or sign-off results.