🧩 Chip Design (VLSI) Labs

VL01 · Sem 3 · Digital logicLogic gates in VerilogDescribe basic gates in Verilog, synthesise them and verify the truth table. VL02 · Sem 3 · Digital logicHalf adder and full adderBuild adders from gates and verify all input combinations. VL03 · Sem 4 · Digital design4-bit ripple-carry adderAdd two 4-bit numbers and check the carry out. VL04 · Sem 3 · Digital logicMultiplexers (2:1 and 4:1)Select one of several inputs with a multiplexer. VL05 · Sem 3 · Digital logic3-to-8 decoderTurn a 3-bit code into one active output line. VL06 · Sem 4 · Digital designPriority encoderFind the highest active request line. VL07 · Sem 4 · Digital designMagnitude comparatorCompare two 4-bit numbers. VL08 · Sem 4 · Computer architecture4-bit ALUBuild an ALU with add, subtract, AND and XOR, plus a zero flag. VL09 · Sem 4 · Digital designD flip-flop with synchronous resetStore a bit on each rising clock edge. VL10 · Sem 4 · Digital design4-bit counter with enableCount clock edges and flag the terminal count. VL11 · Sem 4 · Digital designUp/down counterCount up or down under control of an input. VL12 · Sem 4 · Digital designShift register (serial in, parallel out)Shift bits in one per clock and read them in parallel. VL13 · Sem 5 · VLSI designLFSR pseudo-random generatorGenerate a pseudo-random sequence with a linear-feedback shift register. VL14 · Sem 5 · VLSI designSequence detector (FSM) for 1011Detect the bit pattern 1011 in a serial stream with a finite-state machine. VL15 · Sem 5 · VLSI designTraffic light controller FSMBuild a Moore machine with timed states. VL16 · Sem 5 · VLSI designClock divider and PWM generatorGenerate a slower clock and a PWM signal from a counter. VL17 · Sem 5 · VLSI designGray-code counterCount so that only one bit changes per step. VL18 · Sem 3 · Digital logicEven parity generatorCompute a parity bit for error detection. VL19 · Sem 6 · SoC designUART transmitterSerialise a byte with start and stop bits in hardware. VL20 · Sem 6 · Computer architectureAccumulator (register + adder datapath)Build the datapath at the core of a simple CPU.