VL10 · Sem 4 · Digital design
4-bit counter with enable
Aim: Count clock edges and flag the terminal count.
🧪 Live simulation🧊 Real-time 3D bench⚠ Simulated values, not physical measurements
🔬 Virtual lab
Starting the lab…
📘 Theory
A register plus an adder makes a counter. The asynchronous reset is converted to synchronous logic for this simulation. tc goes high at 15, used to cascade counters.
q⁺ = q + 1 (when en)
🧰 Apparatus (virtual)
- Yosys
- simulator
📝 Procedure
🎤 Viva questions
How do you build a counter that counts to 9 (decade)
Reset to 0 when q reaches 9.
What is a ripple counter
Each flop clocks the next: cheap but slow and glitchy.
🛡️ Safety
Software only. Area and timing use generic teaching assumptions; they are not silicon measurements or sign-off results.