VL09 · Sem 4 · Digital design
D flip-flop with synchronous reset
Aim: Store a bit on each rising clock edge.
🧪 Live simulation🧊 Real-time 3D bench⚠ Simulated values, not physical measurements
🔬 Virtual lab
Starting the lab…
📘 Theory
always @(posedge clk) describes a flip-flop: the output takes the input value only at the clock edge. Non-blocking assignment (<=) models all flops updating together.
q⁺ = d (at the rising edge)
🧰 Apparatus (virtual)
- Yosys
- simulator
📝 Procedure
🎤 Viva questions
What are setup and hold times
How long d must be stable before and after the edge.
Why use non-blocking assignments in sequential logic
So all registers update simultaneously, as in hardware.
🛡️ Safety
Software only. Area and timing use generic teaching assumptions; they are not silicon measurements or sign-off results.