VL03 · Sem 4 · Digital design
4-bit ripple-carry adder
Aim: Add two 4-bit numbers and check the carry out.
🧪 Live simulation🧊 Real-time 3D bench⚠ Simulated values, not physical measurements
🔬 Virtual lab
Starting the lab…
📘 Theory
Vectors ([3:0]) group bits. The + operator lets synthesis build the adder; the logic depth (and so the delay) grows with the number of bits.
{cout, s} = a + b + cin
🧰 Apparatus (virtual)
- Yosys
- simulator
📝 Procedure
🎤 Viva questions
How is overflow detected for signed numbers
Carry into the sign bit differs from carry out.
Why does depth matter
It sets the maximum clock frequency.
🛡️ Safety
Software only. Area and timing use generic teaching assumptions; they are not silicon measurements or sign-off results.