VL02 · Sem 3 · Digital logic

Half adder and full adder

Aim: Build adders from gates and verify all input combinations.

🧪 Live simulation🧊 Real-time 3D bench⚠ Simulated values, not physical measurements

🔬 Virtual lab

Starting the lab…

📘 Theory

A half adder gives sum = a ⊕ b and carry = a·b. A full adder adds a carry-in: sum = a ⊕ b ⊕ cin, cout = ab + cin(a ⊕ b). Full adders chained together make multi-bit adders.

S = A ⊕ B ⊕ Cin · Cout = AB + Cin(A ⊕ B)

🧰 Apparatus (virtual)

Yosys
simulator

📝 Procedure

Synthesise and count the cells
Check all eight rows
Compare with the hand-drawn circuit
Rewrite using the + operator and compare cell counts

Observations and result (kept on this device)

🎤 Viva questions

Why is a ripple-carry adder slow for many bits

Each carry waits for the previous stage.

What is a carry-lookahead adder

It computes carries in parallel from generate and propagate signals.

🛡️ Safety

Software only. Area and timing use generic teaching assumptions; they are not silicon measurements or sign-off results.