VL01 · Sem 3 · Digital logic
Logic gates in Verilog
Aim: Describe basic gates in Verilog, synthesise them and verify the truth table.
🧪 Live simulation🧊 Real-time 3D bench⚠ Simulated values, not physical measurements
🔬 Virtual lab
Starting the lab…
📘 Theory
Continuous assignments (assign) describe combinational logic. Synthesis maps each expression to library cells; the simulator then checks every input combination against the expected output.
y = a·b, a + b, a ⊕ b, ¬(a·b)
🧰 Apparatus (virtual)
- Yosys (in the browser)
- gate-level simulator
- waveform viewer
📝 Procedure
🎤 Viva questions
Why is NAND called universal
Any logic function can be built from NAND gates alone.
What does synthesis do
It turns RTL into a netlist of real cells.
🛡️ Safety
Software only. Area and timing use generic teaching assumptions; they are not silicon measurements or sign-off results.