VL19 · Sem 6 · SoC design
UART transmitter
Aim: Serialise a byte with start and stop bits in hardware.
🧪 Live simulation🧊 Real-time 3D bench⚠ Simulated values, not physical measurements
🔬 Virtual lab
Starting the lab…
📘 Theory
A small FSM loads a byte into a shift register framed by a start bit and stop bit, then shifts it out one bit per baud tick (here one clock per bit). This is the core of every UART IP.
frame = 0 · d₀…d₇ · 1
🧰 Apparatus (virtual)
- Yosys
- simulator
📝 Procedure
🎤 Viva questions
Why send LSB first
It is the RS-232 convention, and shift registers do it naturally.
What does busy prevent
Loading a new byte mid-frame.
🛡️ Safety
Software only. Area and timing use generic teaching assumptions; they are not silicon measurements or sign-off results.